Hiring Design and verification Engineer for Chennai location:
Require Skill Set:
• Design & Verification Engineer
• System Verilog(SV)
• Chip level/Block level Verification
• ASIC
• Protocols – AXI, AHB, AMBA, I2C, SPI, USB, UART, etc
• OVM, UVM, RVM methodologies
Experience : 2 to 10 years
Notice Period :20 Days joining
Please send your resumes to resume@clansys.in mentioning "Design Engineer" in subject line.
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